5.2-GHz 射頻CMOS頻率合成器
An Agile 5.2-GHz RF CMOS Frequency Synthesizer
Date Issued
2004
Date
2004
Author(s)
Lu, Chia-Hsiang
DOI
en-US
Abstract
Wireless communication has undergone an incredible development over last few years, and it’s gradually replacing the cable communication to become the most important part of the modern world. The growing wireless LAN market has generated increasing interest in technologies enabling higher data rates and capacity than initially deployed systems.
A 5.2-GHz PLL-based frequency synthesizer for wireless LAN applications is presented in this thesis. This PLL employs an adaptation scheme for low noise and fast settling. Adaptive bandwidth charge-pump relaxes the design tradeoffs between spurs level and settling time. The adaptation consists of tuning the charge-pump current by the phase error between output and reference frequency. The tracking capability is enhanced by extending loop bandwidth and a low phase noise clock signal is generated by a narrow loop bandwidth. The oscillator is implemented by the hallow-coil spiral inductors. The frequency divider adopts pulse-swallow architecture and uses source-coupled logic to reduce the switching noise. Circuit techniques were used to achieve low-power dissipation. The frequency synthesizer has been fabricated in a 0.18-μm CMOS technology and operates at 5.2 GHz while consuming 20 mW from a 1.8-V supply.
Subjects
鎖相迴路
頻率合成器
無線區域網路
frequency synthesizer
PLL
wirelessLAN
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-93-R91943083-1.pdf
Size
23.31 KB
Format
Adobe PDF
Checksum
(MD5):65e391effbabf7ec075a6839fb43f506