System-Level Performance and Power Optimization for Memory and Storage Subsystems in Smart Personal Devices
Date Issued
2015
Date
2015
Author(s)
Lin, Ye-Jyun
Abstract
As the mobile computing speed rapidly grows, a variety of applications in the personal devices have been made possible. The evolution of personal devices presents new challenges on the memory and storage subsystems. When multiple applications run together, the memory contention among applications prolongs memory access time, which can exacerbate the long-existing memory wall problem. The long memory access latency also results in unnecessary leakage waste of the processing unit due to the memory stall. To provide high reliability for the mobile devices, applications generate bulk storage synchronous writes, which reduces the benefits of the DRAM buffer cache and degrades the user experience of the personal devices. In this thesis, we focus on the optimization for both memory and storage subsystems in smart personal devices. For the memory system, we propose a hierarchical memory scheduler to reduce the impacts of concurrent memory accesses from different applications with fairness guarantee. To reduce the leakage waste of the processing units due to the long memory latency, we propose a memory access aware power gating mechanism which makes the power gating decisions to those units judiciously. For the storage system, we adopt a hierarchical DRAM and PCM buffer cache to reduce the impacts of synchronous storage writes. Based on the hierarchical buffer cache architecture, we propose the buffer cache management policies to improve the user experience of the personal devices.
Subjects
Smartphone
Memory Scheduler
Power Gating
Buffer Cache
Type
thesis
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