Simulation Study of Vertical Pillar Transistor and Ge Gate-All- Around FET
Date Issued
2012
Date
2012
Author(s)
Yin, Yu-Chun
Abstract
For next generation highly-integrated DRAMs, 4F2 cell array structure composed of a capacitor stacked vertically on a cell transistor is required. Vertical pillar transistor (VPT) is regarded as the most promising candidate for cell transistor in the 4F2 cell array architecture due to its excellent gate controllability which enhances the subthreshold characteristics. This cell transistor also shows excellent static retention characteristic, but the dynamic retention characteristic still need much improvement due to the floating body effect in cell transistor. We discuss the physical mechanism of floating body effect in the vertical pillar transistor and propose solutions: 1. to minimize GIDL current 2. to lower the height of the hole barrier between the body and the bit line by using SiGe layer at bottom source/drain. With aggressive device scaling, junctionless transistor can be applied when the body of semiconductor is thinner than 20 nm allowing for full depletion condition in the channel region as the device is turned off. We investigate the GIDL phenomena by simulation and demonstrate an extremely low leakage junctionless VPT with partially recessed drain design. The GIDL is well suppressed and the dynamic retention characteristic is also improved due to the suppressing BJT parasitic current during the variation of bit line bias.
In the second part of the research, we simulate a new kind of advanced device, Ge gate-all-around FET. The fabricated triangular p-channel Ge FET with fin width (Wfin) of 52nm and Lg of 183nm has Ion/Ioff = 105, SS= 130mV/dec, and Ion=235 uA/um at -1V. Based on TCAD simulations and modeled by analytical solution, the triangular channel has better electrostatic control than the conventional rectangular FinFET. By proper scaling of the fin size, EOT, and Dit, further enhancements can be expected.
Subjects
floating body effect
vertical pillar transistor
junctionless transistor
Ge Gate-All- Around FET
Type
thesis
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