Time-mode Sigma-Delta Interface Circuit for Capacitive Sensors
Date Issued
2014
Date
2014
Author(s)
Yang, Tsung-Jung
Abstract
This thesis illustrates the design and implementation of interface circuits for capacitive sensors. The interface circuits perform femto farad resolution at typical sampling rate, which is designed for measuring the change of capacitance under physical change. With linear corresponding relationship between capacitance and output digital code, the interpolation is available in capacitance calculation. By using a standard TSMC 0.18-μm CMOS process, there are two circuits implemented and the functions are verified in measurement results.
Firstly, time-mode approach is introduced to provide a solution suitable for process migration. A sigma-delta modulator is employed to achieve high resolution and the relationship between input and output digital code is linear. The proposed sensor interface is simply composed of a charge pump and a time-mode sigma-delta modulator to reduce the need for traditional analog building blocks as much as possible. Secondly, the multi-bit architecture and additional power-saving techniques are applied to maintain overall performance while reducing the power consumption by half. With the digital output generated form the fabricated chip, the raw data can be easily collected with a logic analyzer and then processed directly with MATLAB on a computer. The chip areas are both 0.68*0.68 mm2. Operated at a 1.2-V supply voltage, the fabricated circuits consume average power of 817 μW and 360 μW and achieve an effective number of bits (ENOB) of 8.8 and 9.07 and figure-of-merit (FoM) of 114.5 pJ/step and 41.7 pJ/step, respectively.
Subjects
電容式感測器
介面電路
時間模態
三角積分調變器
Type
thesis
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