Escape routing for staggered-pin-array PCBs
Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal Volume
32
Journal Issue
9
Pages
1347-1356
Date Issued
2013
Author(s)
Abstract
To accommodate the ever-growing pin number of complex printed circuit board (PCB) designs, the staggered pin array is introduced for modern designs with higher pin density. However, the escape routing for staggered pin arrays, which is a key component of PCB routing, is significantly different from that for grid arrays. This paper presents a routing algorithm for the escape routing for staggered-pin-array PCBs. We first analyze the properties of staggered pin arrays, and propose an orthogonal-side wiring style that fully utilizes the routing resource of the staggered pin array. A linear programming/integer linear programming-based algorithm is presented to solve the staggered-pin-array escape routing problem. Experimental results show that our approach successfully routes all test cases efficiently and effectively.
Type
journal article