A Two-level Test Data Compression and Test Time Reduction Technique for SOC
Date Issued
2005
Date
2005
Author(s)
Liaw, Yu-Te
DOI
en-US
Abstract
In SOC era, long test time and large test data volume are two serious problems. In this thesis, a two-level test data compression technique is presented to reduce both the test data and the test time for System on a Chip (SOC). The level one compression is achieved by selective-Huffman coding for the entire SOC. The level two compression is achieved by broadcasting test patterns to multiple cores simultaneously. Experiments on the d695 benchmark SOC show that the test data and test time are reduced by 64% and 35%, respectively. This technique requires no change of cores and hence provides a good SOC test integration solution for the SOC assemblers.
Subjects
測試資料壓縮
測試時間壓縮
系統晶片測試整合
Test data compression
Test time compression
SoC test integration
Type
thesis
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ntu-94-R92943110-1.pdf
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