High-performance three-dimensional on-chip inductors in SOI CMOS technology for monolithic RF circuit applications
Journal
IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers
Pages
591-594
Date Issued
2003-06
Author(s)
Kim, Jonghae
Plouchart, Jean-Olivier
Zamdmer, Noah
Fong, Neric
Tan, Yue
Jenkins, Keith A.
Sherony, Melanie
Groves, Robert
Kumar, Mahender
Ray, Asit
Abstract
This paper presents high-Q and high-inductance-density on-chip inductors fabricated on high-resistivity substrate (HRS) using a 0.12 μm SOI CMOS technology with 8 copper metal layers. A peak Q of 52 is obtained at 5 GHz for a 0.6 nH STP (Single-turn, multiple metal levels in Parallel) inductor. An inductance density of 5302 fH/μm2 is obtained for a 42 nH MTS (Multi-turn, multiple metal layers in Series) inductor.
Event(s)
2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium
Other Subjects
Electric inductors; Electric network analysis; Q factor measurement; Semiconductor device models; System on chip (SOC) technology; CMOS integrated circuits
Type
conference paper