Design of Power Splitter and Combiner for 60 GHz Applications
Date Issued
2010
Date
2010
Author(s)
Chang, I-Chih
Abstract
Using phased-array system is the trend of the future communication system, since phased array has benefit of improvement signal-to-noise ratio (SNR), improvement equivalent isotropically radiated power (EIRP), and spatial interference cancellation. The signal needs to be evenly split to each chain on transmitter and to be combined from each chain on receiver, since phased-array system is consisted of multiple transceivers and antennas. Therefore power splitter and combiner components are required.
In this thesis, the passive power splitter, passive power combiner, and active power splitter are implemented by using complementary metal-oxide semiconductor (CMOS) process. The thesis is comprised of five chapters. The brief introduction of phased-array system is shown in chapter 1. The principle of power splitter and combiner, and design consideration on CMOS process are shown in chapter 2.
In chapter 3, the one-to-four power splitter and four-to-one power combiner have been designed. Both of two circuits are operated in 60-GHz band, and implemented by using TSMC 65-nm CMOS process. The circuits consisted of Wilkinson power splitter/combiner and buffer amplifier. The thin-film microstrip line is used to match element for reducing effect of lossy substrate.
The measured insertion gain of one-to-four power splitter at output port 1 and port 2 are -0.9 to 3 dB and 2.9 to 4.9 dB, respectively. The operation frequency is from 57 GHz to 65 GHz. The minimum measured isolation is 16.7 dB and the minimum measured OP1dB is -3.67 dBm.
The measured insertion gains of four-to-one power combiner at input port 1 and port 2 are 4.9 to 11.2 dB and 4.7 to 11.1 dB, respectively. The operation frequency is from 57 GHz to 65 GHz. The minimum measured isolation is 19.3 dB and minimum measured OP1dB is -4.83 dBm. The reason of inducing differences between measurement and simulation is discussed in this chapter. Both of two circuits are re-designed and re-simulated.
In chapter 4, the one-to-four active power splitter has been designed. The proposed circuit is operated in 60-GHz band, and implemented by using TSMC 90-nm CMOS process. The current is used to split power in the design. The proposed circuit has advantages of wideband frequency response and small chip size. The measured two way insertion gains are balanced and all above 0 dB under VDD is 2 V. The measured OP1dB is near 0 dBm. To the author’s knowledge, the circuit structure is the first demonstration of 60-GHz four-way active power splitter in a standard CMOS technology.
In chapter 5, the brief conclusion of the thesis is given.
Subjects
Phased-array
CMOS
passive power splitter and combiner
active power splitter
60-GHz application
Type
thesis
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