Thermal-aware router-sharing architecture for 3D network-on-chip designs
Journal
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Pages
1087-1090
Date Issued
2010
Author(s)
Abstract
In this paper we propose a router-sharing architecture for 3D NoC which outperforms existing 3D NoC designs under thermal impacts. According to thermal simulations, in conventional designs, the routers on the top layers far from the heat sink have to be disabled frequently to avoid thermal emergency. Therefore, the proposed architecture removes all routers on the top layers and uses only buses to connect top-layer PEs to the routers underneath. At 85 °C, our architecture receives 1.4 times as many packets when compared to conventional designs. If the temperature constraint is set at 80 °C, our architecture can receive 2 times as many packets. In addition, this new architecture is energy-efficient because the average number of hops is reduced. © 2010 IEEE.
Subjects
3D ICs; 3D Network-on-chip; network performance analysis; thermal analysis
SDGs
Other Subjects
3-D ICs; Average number of hops; Conventional design; Energy efficient; Network on chip; network performance analysis; Network-on-chip design; NoC design; Proposed architectures; Thermal emergencies; Thermal impacts; Thermal simulations; Computer architecture; Design; Energy efficiency; Network architecture; Network performance; Servers; Thermoanalysis; Three dimensional; VLSI circuits; Routers
Type
conference paper