A CMOS Broadband Receiver for 100-Gb/s Ethernet System
Date Issued
2010
Date
2010
Author(s)
Wu, Ke-Chung
Abstract
The 100-Gb/s Ethernet (100GbE) is the next generation''s Ethernet standard, which aims at the applications of both server computing and network aggregation. In this dissertation, a 2 × 25-Gb/s receiver for 100GbE has been implemented in 65-nm CMOS technology. Although only 2 channels are implemented, this receiver provides exactly the same operation as a 4-channel one while dealing with independent channels. It is mainly composed of three critical components of a wireline receiver, limiting amplifier, clock and data recovery (CDR), and demultiplexer (DMUX). Two identical 25-Gb/s limiting amplifiers provide high-gain and broad-bandwidth to achieve a large output swing with minimum inherent jitter. A novel regulation mechanism is applied to the limiting amplifiers to minimize its gain and bandwidth variations. Two low-power full-rate CDRs employ mixer-type linear phase detectors and automatic frequency locking techniques. The phase detector achieves high-speed operation by mixing the clock with the data-transition pulses, providing output proportional to the phase error. The frequency acquisition loop utilizes the data phases rather than the clock phases to distill the frequency difference, and no external reference is used in this design. A high-speed 2:5 DMUX circuit (with a built-in clock generator) is also integrated. The fractional-ratio demultiplexing is realized by an efficient two-step conversion scheme. This two-channel receiver achieves BER < 10^−12 with 20-mVpp input sensitivity while consuming a total power of 510 mW from a 1.2-V supply.
Subjects
100 GbE
bandgap reference
bit error rate (BER)
clock and data recovery (CDR)
clock multiplication unit (CMU)
demultiplexer (DMUX)
deskew circuit
divider
jitter tolerance
limiting amplifier (LA)
Type
thesis
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