Formal modeling and verification for Network-on-chip
Journal
1st International Conference on Green Circuits and Systems, ICGCS 2010
Pages
299-304
Date Issued
2010
Author(s)
Abstract
A model checking based formal verification procedure is developed to verify and validate the routing microarchitecture in a Network-on-chip (NoC) communication infrastructure. Specifically, four crucial properties of an NoC router, namely, mutual exclusion, starvation freedom, deadlock freedom, and conditions for traffic congestions are investigated. Given a recently proposed bi-directional channel direction control protocol, guidelines for constructing formal models of an NoC router are proposed, and minimal formal models essential for verifying these four properties are analyzed. A popular formal verification model checking tool State Graph Manipulators (SGM) is applied to perform the verification task. Results obtained through formal verification of these four properties provide useful insights to refine the protocol design. © 2010 IEEE.
SDGs
Other Subjects
Bi-directional channels; Communication infrastructure; Deadlock freedom; Formal model; Formal modeling and verification; Formal verification procedures; Formal verifications; Micro architectures; Mutual exclusions; Network on chip; Protocol design; Starvation-freedom; State graphs; Verification task; Model checking; Servers; Traffic congestion; VLSI circuits; Routers
Type
conference paper