A 1GS/s 6-bit 48mW A/D Converter
Date Issued
2007
Date
2007
Author(s)
Chen, I-Ching
DOI
en-US
Abstract
A 1 GS/s 6-bit CMOS two-step ADC using fast-settling method and through timing rearrangement is demonstrated in a standard 0.13-μm CMOS process. The proposed method shortens the slew time of OPAMP in MDAC and the timing arrangement makes the circuits operated more efficient. The prototype circuit exhibits an INL of +0.3/-0.3 LSB and a DNL of +0.49/-0.49 LSB. The SNDR and SFDR achieve 31.3 and 49.2 dB at 1 GS/s for Nyquist input frequency. The ADC consumes 50 mW at 1.2V supply and occupies an active chip area of 0.16 mm2.
Subjects
類比數位轉換器
兩階段式
時間交錯
低功率
ADC
Two-step
Time-interleave
low power
Type
thesis
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ntu-96-R93943111-1.pdf
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