Low Power Test Pattern Generation for Scan-based Testing
Date Issued
2008
Date
2008
Author(s)
Lin, Hsiu-Ting
Abstract
Power dissipation is a serious problem for scan-based testing because it can cause catastrophic damaging of circuit under test or degrade power integrity during test. This thesis proposes two effective low power automatic test pattern generation (ATPG) flows to reduce the peak power during scan-based testing.he first technique is CASPR, Capture and Shift Power Reduction. It includes parity backtrace, confined fault propagation, dynamic controllability, X-filling procedure for both shift and capture, and test regeneration and all techniques of CASPR can be integrated to conventional test generation flow. The experimental data on ISCAS89 benchmark circuits show that CASPR succeed to reduce the peak capture power by 31% and peak shift power by 26% in single stuck at fault test pattern generation with only 11.2% test length overhead.he second technique called CASTR, Capture and Shift Toggle Reduction, proposes a new low power test generation flow to handle the exceeded power noise problem during testing. Exceeded power noise can degrade power integrity and increase the probability of yield loss. We combine both pseudo boolean optimization and random simulation flow into X-Constraint ATPG. Moreover, a modified test regeneration procedure based X-identification techniques is also introduced to further improve the results. In the experimental results, we can reduction the peak shift flip-flop transition count (FFTC), which is showed to be highly correlation with power noise, by 35% with negligible test length overhead by CASTR. The same technique can also be applied for peak capture FFTC reduction.
Subjects
low power automatic test pattern generation (LP-ATPG)
Scan-based Testing
X-filling
power noise problem
Pseudo Boolean Constraint (PBC)
Type
thesis
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