A 12-bits 50MS/s Pipelined-SAR ADC in 0.18μm CMOS Technology
Date Issued
2014
Date
2014
Author(s)
Lu, Wei-Jin
Abstract
Recently, high resolution and low power analog-to-digital converters (ADCs) have been widely utilized in mobile communication devices. In this thesis, a two-stage pipelined-SAR ADC is proposed.
The conventional two-stage Pipelined-SAR ADC uses half-gain and half reference to alleviate the operational amplifier (OP-amp) design complexity and reduce the power consumption. Because of fewer PADs, we significantly reduce the chip area compared to both traditional pipelined ADC and SAR ADC. Because of the process variation considerations, the unit capacitance should not be reduced. Therefore, we use the smallest MIM cap (about 20fF) provided from TSMC 0.18μm CMOS technology the first-stage capacitor array. The edge effect is suppressed to improve the matching accuracy by a modified high spurious-free dynamic range (SFDR) common centroid symmetry capacitor array layout. In additional, we use MOM cap in the second-stage capacitor array for smaller capacitance (about 2.5fF) to reduce the power consumption of OP-amp and switching energy of capacitor array. In each capacitor switching strategy, the modified monotonic switching procedure is adopted to reduce the average switching energy and alleviate the signal-dependent dynamic offset caused by the variation of input common-mode voltage. Besides, we generate two-phase non-overlapping clock signal and asynchronous control signal with external tunable sampling width, to make clock frequency lower than sampling rate and alleviate the performance degradation induced by bondwire parasitic inductance in sampling phase.
The 12-bit, 50-MS/s two-stage Pipelined-SAR ADC implemented in a 0.18-μm 1P6M CMOS technology. Under 1.8-V supply voltage, the ADC consumes 5.4 mW with 2.4Vp-p input range. The peak ENOB and SFDR is 7.41 bits and 56.93 dB. The FOM is 639.44fJ/conversion-step.
Subjects
十二位元
管線式
逐漸趨近式
類比數位轉換器
Type
thesis
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