Research on Linearization Technique for CMOS Power Amplifier
Date Issued
2010
Date
2010
Author(s)
Hsu, Yu-Chung
Abstract
In this dissertation, a modified cold-FET pre-distortion linearizer is proposed to improve the linearity of the millimeter-wave CMOS power amplifiers. The previous reported cold-FET linearizer as applied to a 40 GHz power amplifier with a low-loss built-in linearizer in GaAs HEMT technology [6]. However, the effect of the linearizer is not good enough when we try to transplant the technique to 60 GHz using CMOS technology. Therefore, we investigate the operation detail of the linearizer and propose a modified linearizer by adding a delay line. Besides, a bias optimization method that can effectively guarantee the linearity of specific cascode device for power amplifier application is also presented.
A 60GHz cascode power amplifier with modified linearizer is then fabricated under 90-nm LP CMOS technology and fully characterized to enhance its linearity which demonstrated by its extremely well OP1dB. The measurement results of the power amplifier show a power-added-efficiency at OP1dB up to 14% while maintaining 15 dB small signal gain, 13.7 dBm OP1dB and 15.4 dBm Psat. It is the highest power-added-efficiency at OP1dB for millimeter-wave CMOS power amplifiers which ever been published.
Subjects
Power Amplifier
PA
High PAE
Linearizer
V-band
Pre-distortion
Linearization Technique
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