Asymmetric keep-out zone of through-silicon via using 28-nm technology node
Journal
IEEE Electron Device Letters
Journal Volume
36
Journal Issue
9
Pages
938-940
Date Issued
2015
Author(s)
Yan, J.-Y.
Jan, S.-R.
Huang, Y.-C.
Lan, H.-S.
Huang, Y.-H.
Hung, B.
Chan, K.-T.
Huang, M.
Yang, M.-T.
Abstract
The performance variation caused by the stress field near a through-silicon via (TSV) is measured using 28-nm node devices across 12-in wafers. The TSV is fabricated by a via-last process. The back-end-of-line dielectrics on TSV cause the asymmetric stress field, i.e., the absolute value of radial stress ( |σr| does not equal to that of tangential stress ( |σθ|on silicon and leads to the asymmetric keep-out zone (KOZ), different from previously reported. A modified KOZ model with the asymmetric radial and tangential stress field is proposed and verified by 3-D finite-element analysis simulation and experiment data. The physics behind the asymmetry is also described. Comparable KOZ size for nFETs and pFETs is observed.
SDGs
Type
journal article