Nanowire-Aware Routing Considering High Cut Mask Complexity
Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal Volume
36
Journal Issue
6
Pages
964-977
Date Issued
2017
Author(s)
Su, Y.-H.
Abstract
1-D nanowires are one of the most promising next-generation lithography technologies for 7 nm process node and beyond. The 1-D nanowire process first constructs a 1-D nanoarray through template synthesis followed by line-end cutting with additional cut masks. To achieve better yield and manufacturability, the cut patterns shall satisfy specified restricted design rules, and thus it is desirable to develop a novel routing methodology to better address the challenges arising from cut patterns. In this paper, we propose the first nanowire-aware routing system, considering high cut-mask complexity based on a two-pass, bottom-up multilevel routing framework. Experimental results show that our nanowire-aware router can effectively and efficiently reduce cut numbers, cut spacing violations, and line-end extension length.
Type
journal article