A Priority Assignment Strategy of Processing Elements over an On-Chip Bus
Date Issued
2006
Date
2006
Author(s)
Tang, Song-Jian
DOI
en-US
Abstract
The number of bus transactions in multimedia SoC grows significantly in recent years. Because of different timing requirements for different applications, how to find a proper priority assignment for processing elements (PEs) of SoC becomes very challenging. In this thesis, we first show that the priority assignment problem with one unique priority for each PE is NP-hard. When each bus transaction can have one unique priority, we propose an optimal priority assignment algorithm for a given bus transaction graph. We then propose a priority assignment strategy based on simulated annealing (SA) for PEs, where bus arbitration is done in a priority-driven fashion. The objective is to minimize the number of priorities needed for each PE and to satisfy the performance requirements of applications. The experimental results show some encouraging results in priority assignment.
Subjects
晶片匯流排
優先權分配策略
on-chip bus
priority assignment strategy
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-95-R93922032-1.pdf
Size
23.31 KB
Format
Adobe PDF
Checksum
(MD5):e702a4aecb12bf21eecb3f4a34530132