Design and Implementation of CMOS Dual-Loop Frequency Synthesizers
Date Issued
2005
Date
2005
Author(s)
Chi, Ta-Sheng
DOI
en-US
Abstract
Wireless communication has undergone an incredible development over last few years, and it's gradually replacing the cable communication to become the most important part of the modern world. The growing wireless LAN market has generated increasing interest in technologies enabling higher data rates and capacity than initially deployed systems.
The dual-loop type frequency synthesizers for wireless
applications are presented in this thesis. The first chip is
composed of phase frequency detector (PFD), charge pump (CP),
LC-tank voltage-controlled oscillator (VCO), and ring-type
voltage-controlled oscillator, single-sideband mixer (SSB mixer), and multi-modulus driver. The required low-pass filter is provided by off-chip components in this design. The synthesizer employs a dual-loop architecture to realize a monolithic design with more optimal trade-off among phase noise, channel spacing, reference frequency and settling time compared to the conventional integer-N phase-locked loop architecture.
The architecture of the second chip is based on dual-loop type synthesizer. However, the offset frequency is generated by a direct digital synthesizer. The use of the DDS makes this synthesizer potentially suitable for direct frequency modulation, without requiring any pre-emphasis and digital calibration loop that are instead necessary in fracional-N PLL.
Subjects
頻率合成器
鎖相迴路
雙迴路
直接數位合成
frequency synthesizer
PLL
dual-loop
DDS
Type
thesis
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