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A 3D Memory Wafer To Wafer Stacking Algorithm
Date Issued
2014
Date
2014
Author(s)
Mao, Rui
Abstract
As the process technology continues to evolve, IC become smaller and high performance, and the cost become higher. A 3D-IC uses Through Silicon Via (TSV) is an emerging technology, higher performance, and lower power consumption compared to planar ICs. However stacking yield is a problem of 3D-IC.
In this thesis, we propose a new algorithm using improved from the hungarian method of assignment on the three-dimensional memory for wafer to wafer stacking. Our results show that our algorithm can be a reasonable amount of time, given the higher stacking yield.
In this thesis, we propose a new algorithm using improved from the hungarian method of assignment on the three-dimensional memory for wafer to wafer stacking. Our results show that our algorithm can be a reasonable amount of time, given the higher stacking yield.
Subjects
三維記憶體
晶圓到晶圓
堆疊
演算法
Type
thesis
File(s)
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Name
ntu-103-R00943152-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):4fba17a73fce69b70b7b0435e9cea291