Scan Test Pattern Generation Considering Test Power, Compressibility, and IR-Drop Effects
Date Issued
2010
Date
2010
Author(s)
Wu, Meng-Fan
Abstract
Scan testing is a widely used test methodology in the industry and the automatic test pattern generation (ATPG) problem has been studied for several decades.Although ATPG is a classical problem, modern high operating frequency, low-power, and high complexity circuit designs have posed new challenges. Thus, during test pattern generation, in addition to fault coverage and test pattern count, one has to consider test power dissipation, test pattern compression, and excessive IR-drop effects on at-speed scan testing. If we can consider above issues while generating test patterns, the test set quality could be improved.
In this dissertation, we propose several algorithms and techniques to consider test power dissipation, test compressibility, and IR-drop effects in ATPG. This dissertation starts with a new technique, which aims at reducing test power and IR-drop effects during the whole scan test application process. Next, we propose an efficient and effective flow to alleviate launch cycle IR-drop effects by minimizing launch cycle switching activity in the test compression environment. Finally, to improve the IR-drop estimation accuracy, we propose a scalable quantitative measure of IR-drop effects which improve the accuracy by considering the power grid structure.
Subjects
VLSI Testing
Low-Power Test
IR-Drop-Aware Test
Test Compression
Type
thesis
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