THE STUDY OF DIGITAL TV SYSTEM CORE DESIGN AND IMPLEMENTATION
Date Issued
2004
Date
2004
Author(s)
Lin, Shyh-Feng
DOI
en-US
Abstract
This dissertation presents four video processing techniques that are essential for real-time digital TV systems.
The MPEG2 video decoder is the most computationally intensive part of a digital TV system. A dedicated accelerator is usually designed for solve this problem. However simulation on EDA tool platform is very time-consuming, that is not corresponded to the concept of time to market. In the first part of this dissertation, a fully pipeline MPEG2 video decoder architecture and an efficient test bitstream design methodology are presented. Each necessary function is selected and the corresponding symbols are inserted into bitstream in the macroblock level; rearrange these macroblock distributions for reducing the macroblocks numbers. It takes about 7 hours to simulate a full functionality of MPEG2 video decoder at RTL deign stage on the Ultrasparc-IITM 360Mhz CPU, which is 50 times faster than using those conformance bitstreams.
Video decoder is always necessary, if the analog video still exist in the world. Proposed architecture of Video Decoder is presented in the second part. It consists of the analog front-end, All Digital Line Lock, 3D Adaptive Y/C Separator, Burst PLL, and Demodulator. Jitter effect could be eliminated when All Digital Line Lock is adopted. The 3D adaptive comb filter improves the video quality of Y/C Separation. Burst PLL could lock sine wave both in 3.58 MHz and 4.43 MHz for demodulating the accurate chrominance signal. Single clock system and fully digital design could be easy integrated with other systems. The experimental results show that the proposed algorithm and architecture has better performance than previous work.
Comparing the traditional analog TV display, larger size/higher resolution and progressive scan is the trend. Translating the interlaced video to the progressive format is still an open research problem. In the third part, a motion adaptive de-interlacing algorithm is presented. It consists of the ELA-median directional interpolation, same-parity 4-field horizontal motion detection, morphological operation for noise reduction and adaptive threshold adjusting. The edges can be sharper when the ELA-median directional interpolation is adopted. The same-parity 4-field horizontal motion detection detects faster motion and makes more accurate determinations about where objects are going to move. The morphological operation for noise reduction and adaptive threshold adjusting preserve the actual texture of the original objects. The proposed method achieves cost-efficient hardware implementation with low complexity, low memory usage, and high-speed processing capability. The experimental results show that the proposed algorithm is more cost-effective than previous systems.
In several wireless hand-held systems, the finite impulse response (FIR) filters are the indispensable parts among various image/video communication applications to reduce noise and to enhance the specific features. With a given specification, the dedicated filter is designed to fit in the applications and has the least effect of redundancy. At last part, a novel approach for implementing power-efficient finite impulse response (FIR) filters is proposed. The proposed schemes can be adopted in the direct form FIR filter and achieve a large amount of reduction in the power consumption. By using a combination of proposed methods, balanced-modular techniques with retiming and separated processing data flow scheme with modified CSD representation. Experimental results show that the proposed scheme reduce 76% power consumption of the original direct-form structure with slight area overhead.
These techniques can greatly improve the video quality and be suitable implemented for real-time digital TV systems.
Subjects
濾波器
去交錯
數位電視
晶片
Filter
Chip
Deinterlace
VLSI
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-93-D87921029-1.pdf
Size
23.31 KB
Format
Adobe PDF
Checksum
(MD5):ddb3b4332d5999565716bf35a0e8b174