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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing
Details
Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing
Journal
Journal of Low Power Electronic
Journal Volume
3
Journal Issue
2
Pages
206-216
Date Issued
2007-08
Author(s)
CHIEN-MO LI
Chun-Yi Lee
CHIEN-MO LI
DOI
10.1166/jolpe.2007.121
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/334018
Type
journal article
