Intelligent Brain-inspired Human-centric Recognition Algorithm and its Hardware Architecture Design
Date Issued
2012
Date
2012
Author(s)
Chen, Chun-Ting
Abstract
As the technologies continue to evolve, our computers have more and more
computing capacity, which drives a lot of intelligent applications to emerge
like smile shutter, automatic surveillance system, smart car and smart home.
These smart machines can sense the surrounding like human and provide
safety, convenience and efficiency to help human. These intelligent applications
in this thesis are called human-centric applications which based on the
needs of human. In this thesis, we focus on the human-centric recognition
applications,such as face recognition, object recognition and action recognition.
On the other hand, since we are in the era where radio equipped
computers dominate, the amount of multimedia data is growing extremely
fast. Youtube have reported that more than 35 hours of video are being
uploaded to the video-sharing site every minute in 2010. In this rate, we
need to handle over one zettabyte of information annually. Therefore, to
support various intelligent applications and manage this huge amount of
data, we need an efficient and scalable hardware platform to provide the required
computation capability. The ultimate goal is to approach human-like
intelligence. For building an intelligent machine, mimicking the structures
and functions of visual cortex has always been a major approach to implement
a human-like intelligent visual system. In this thesis, we started from
exploring brain’s computing style and architecture, then designed a brainlike
computing system for visual recognition,which can be easily scalable
with the amount of resources for future intelligent applications. The whole system design flow starts from Neocortical Computing (NC) model design,
Neocortical Computing System design and then the real-time human-centric
NC architecture based on FPGA system. NC model provides the functionality
for required intelligent human-centric applications. NC architecture is
an efficient and scalable hardware platform optimized for NC model. And
FPGA system verify the NC system by transforming the NC model into the
specific memory content that can be interpreted by platform. In this thesis,
the main system design strategy is to provide the application diversity and
efficiency as human brains.
At first, we analyze the current NC models and find that they are lack
of the temporal domain integration and thus are hard to explore the object
recognition into time-relevant action recognition. To solve this problem,
inspired from the human brain system’s recurrent information transmission
nature and neuron network research, we proposed a recurrent computing
kernel to integrate the temporal domain action feature information efficiently.
Therefore we could construct an efficient dimension-lifting Reservoir
Kernel which exhibits the property of temporal memory and thus can
integrate the temporal information provided by the HMAX network and
boost up its recognition performances. Experimental results showed that it
can outperform the state-of-the-art HMMSVM method substantially.
Second, for the NC system design of NC model, we analyze the computation
of NC model and state its main problem – massive data access, which
results in power inefficiency, redundant external bandwidth usage, slow response
and no communication scalability. In current computing system,
this problem causes the NC system becomes a memory-bounded system.
To address this issue, inspired from the information forwarding scheme of
neurons, we proposed a Push-based Dataflow (Push-DF) structure using
push-based processing for external memory access reduction and efficient
sparse data forwarding. From the experimental result, the Push-DF in many-core architecture can achieve lower latency, power consumption and
external bandwidth than RISC and GPU. Utilizing push-based processing
greatly reduces the massive external memory access so that our NC system
can break the bottleneck of traditional memory-bounded system. This important
feature provides the communication scalability of our NC system,
which meets the design goal for a scalable brain-mimicking hardware platform.
At last, we utilized the proposed Push-DF structure for designing NC
system and implemented a 8-core NCSoC in FPGA system. Our final implementation
of NCSoC takes 0:179 seconds to recognize a 100×100 image.
In conclusion, NCSoC supports NC model for various intelligent recognition
tasks, and provides better performance, efficiency and scalability over
current computing platform. As a result, it have the potential to support
various intelligent applications and manage huge amount of multimedia data
for future applications.
Subjects
human-centric
recognition
action recognition
hardware design
Type
thesis
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