An all-digital jitter-tolerance measurement technique for CDR circuits
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
59
Journal Issue
3
Pages
148-152
Date Issued
2012-03
Author(s)
Abstract
An all-digital on-chip jitter tolerance measurement technique for clock/data recovery (CDR) circuits is presented. A 6-Gbps CDR circuit with this proposed technique is realized in a 90-nm CMOS process. The measured jitter tolerance by using the testing equipment and the proposed technique correlate within 13% in the frequency range of 178 kHz ∼ 11.3 MHz. The measured peak-to-peak data and clock jitters are 15.56 and 13.3 ps. The power of the CDR circuit is 44.4 mW at a supply voltage of 1.2 V. © 2006 IEEE.
Subjects
All-digital; clock and data recovery; jitter tolerance
Other Subjects
Clocks; Jitter; Timing circuits; All digital; Clock and data recovery; Clock jitters; Frequency ranges; Jitter tolerance; Measurement techniques; Supply voltages; Testing equipment; Clock and data recovery circuits (CDR circuits)
Type
journal article