Development of Module Library for Communication/ Sigal Processing System Chips
Date Issued
1999-07-31
Date
1999-07-31
Author(s)
DOI
882215E002039
Abstract
The project is focused on
developing the parametric module
library and the standard cell libraries
suitable for digital baseband signal
processor design. The designers
assign the parameters to parametric
modules, perform function level
simulations, and immediately get the
corresponding gate-level Verilog
code. With this design methodology
we could drastically reduce the
system design time and prevent
errors made by designers. We
purposed a parametric module class
and several data structure. Based on
these classes, we wrote a series of
parametric modules including many
kinds of logic arrays, high speed
adders/multiplers, and FIR filters.
The library cells are designed using
TSMC 0.6/0.35mm technologies.
Each standard cell library contains
56 frequently used cells. We sized
the transistors in order to operate the
cells in low-voltage conditions and
finally performed an exhaustive test
to garentee the cells meet the
function/performance specifications.
Subjects
module library
cell library
parametric module
Publisher
臺北市：國立臺灣大學電機工程學系暨研究所
Type
report
File(s)![Thumbnail Image]()
Loading...
Name
882215E002039.pdf
Size
898.64 KB
Format
Adobe PDF
Checksum
(MD5):c4b7a4c4e2b4a314df569b9d406d2755