Chessboard Parallel Processing for High Efficiency Video Coding
Date Issued
2014
Date
2014
Author(s)
Chiu, Yu-Siang
Abstract
The next generation video coding standard – High Efficiency Video Coding (HEVC) reduce 50% bitrates compared to H.264/AVC under the same visual quality [1]. The price to be paid for higher coding efficiency is higher computational complexity. As a result, single processer is difficult to be optimized to a satisfactory level. Unlike H.264/AVC, HEVC currently contains several tools like wavefront parallel processing (WPP) and tiles aimed at making the encoder more parallel-friendly. In this paper, we briefly introduce intra and inter prediction and analyze the reason why the utilization of threads cannot be optimized while HEVC enable WPP. The most important, we proposed a new encoding scheme – chessboard parallel processing (CPP). We design a new encoding order that coordinates with new directions of references to improve the utilization of threads. In addition, we compare our reference patterns with WPP and make a detailed analysis of parallelism and coding efficieny. Experiments conducted on a 32-core system show that our implementations achieve higher performance and reduce 41.8% encoding time in average under a well bitrate control.
Subjects
高效率影片編碼
平行處理
多核心處理
Type
thesis
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