A 2.5Gbps burst-mode clock and data recovery circuit
Journal
IEEE Asian Solid-State Circuits
Pages
457-460
Date Issued
2005-11
Author(s)
Abstract
A 2.5Gbps burst-mode CDR circuit is fabricated in 0.18mum CMOS process. The data generator for this CDR circuit is presented with reduced hardware and low power dissipation. The tight timing budget of the clock generator is also relaxed. The bit error rate less than 10 -12 is achieved for a PRBS of 2 31 -1 with 500ppm frequency deviation. The area of the digital core is 0.36mm 2 and the power of 33mW/port is achieved for a 1.8V supply
Type
conference paper