A Low Power Scheduling Method with Dual Supply Voltage and Dual Threshold Voltage
Date Issued
2004
Date
2004
Author(s)
Chang, Szu-Wei
DOI
en-US
Abstract
Dynamic power consumption goes down quadratically with the supply
voltage scaling down. It is naturally for the researchers to scale
down the supply voltage to reduce power consumption. It is also
possible to reduce the power consumption in a design without degrading
the performance by reducing the supply voltage of those cells
o® the critical path. This method is so-called dual/multiple supply
voltage methodology. However, it is also possible to provide
dual/multiple threshold voltage to reduce the power consumption. As
in [1] [2] [3] [4] [5] [6] [8] [7], many researches focus on assigning dual
supply/threshold voltage to gate-level design. In this paper, we proposed
a partitioning methodology with multiple supply voltage and
multiple threshold voltage in behavioral synthesis stage. By considering
multiple voltages and multiple thresholds in higher level of the
design flow, we can explore larger design space of power, area, and
performance. Hence we can optimize the power consumption without
losing circuit e±ciency and area.
And because the scheduling problem has been proven to be a NP
problem, so we can not find optimal solution in polynomial time. To
solve this, we adopt a GA (Genetic Algorithm) based SA (Simulated
Annealing) approach to find an approximation result.
Subjects
合成
低功率
排程
GA-Based SA
synthesis
lowpower
Type
thesis
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