A 0.1-23-GHz SiGe BiCMOS analog multiplier and mixer based on attenuation-compensation technique
Resource
Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE
Journal
Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE
Pages
-
Date Issued
2004-06
Date
2004-06
Author(s)
Tsai, Ming-Da
Lin, Chin-Shen
Wang, Chi-Hsueh
Lien, Chun-Hsien
Wang, Huei
DOI
1529-2517
Abstract
A SiGe BiCMOS broadband mixer and analog multiplier using LC ladder matching networks and attenuation-compensation method were first proposed. This broadband mixer achieves measured conversion gain of 19 dB with a 3-dB bandwidth from 0.1 to 23 GHz. The mixer was fabricated in a commercial 0.35-/spl mu/m SiGe BiCMOS technology and demonstrated the highest gain-bandwidth product of operation among previously reported MMIC mixers. As an analog multiplier, the measured sensitivity is better than 3000 V/W from 0.1 to 25 GHz with 50-/spl Omega/ output impedance. The chip area is 1.5/spl times/1 mm/sup 2/ including testing pad. The performance of this circuit represents a state-of-the-art result of the MMIC broadband mixers using standard silicon-based technologies.
SDGs
Type
journal article
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