A 794Mbps 135mW iterative detection and decoding receiver for 4x4 LDPC-coded MIMO systems in 40nm
Journal
IEEE Symposium on VLSI Circuits
Journal Volume
2015-August
Pages
C102-C103
Date Issued
2015
Author(s)
Abstract
A low-density parity-check (LDPC)-coded multiple-input multiple-output (MIMO) systems with iterative detection and decoding (IDD) chip is integrated in 1.33mm 2 in 40nm CMOS. The maximum gross throughput is 794Mb/s for a 4×4 16-QAM configuration at 288MHz. The chip dissipates 135mW at 0.9V, achieving an energy efficiency of 170pJ/bit. Compared to non-IDD receivers, composed of state-of-the art MIMO detectors and LDPC decoders, this work achieves even higher area and energy efficiencies, despite the improved error performance.
SDGs
Type
conference paper