WNxCy VT Tuning of Split Gate Nanosheet CFETs with Dual Work Function Metals Achieving 0.93 VT Match/ Improved 0.24V Noise Margin/ Record Gain of 61V/V
Part Of
Technical Digest - International Electron Devices Meeting, IEDM
Start Page
1
End Page
4
ISBN (of the container)
979-835036542-9
Date Issued
2024-12-07
Author(s)
Bo-Wei Huang
Chun-Yi Cheng
Wan-Hsuan Hsieh
Yu-Rui Chen
Wei-Jen Chen
Yi-Chun Liu
Min-Kuan Lin
Ying-Qi Liu
Hao-Yi Lu
Yi Huang
Ding-Wei Lin
Abstract
The sophisticated epitaxial growth and device fabrication process of dual-work-function-metal split-gate CFETs are demonstrated for the first time. Multiple P/N junctions are employed to isolate stacked transistors. The effective work function of can be tuned by changing the N2/H2 flow rate during the PEALD process. The ~10nm thick are integrated into GeSi CFET to show the pFET threshold voltage tunability of 500mV. The dual-WFM split-gate CFETs can provide matched . The hold state noise margin of SRAM is expected to be 0.24V at . The voltage transfer curve of a CFET inverter has a record gain of 61V/V among monolithic nanosheet CFETs. The tuning of 300mV is also demonstrated for the nFET.
Event(s)
2024 IEEE International Electron Devices Meeting, IEDM 2024
Publisher
IEEE
Type
conference paper