Skip to main content
English
中文
Log In
Log in
Log in with ORCID
NTU Single Sign On
Have you forgotten your password?
Home
College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Minimizing coupling jitter by buffer resizing for coupled clock networks
Details
Minimizing coupling jitter by buffer resizing for coupled clock networks
Journal
IEEE International Symposium on Circuits and Systems
Journal Volume
5
Pages
V509-V512
Date Issued
2003
Author(s)
Hsiao, Ming-Fu
Malgorzata, Marek-Sadowska
Chen, Sao-Jie
DOI
10.1109/ISCAS.2003.1206333
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-0037743888&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/303245
http://ntur.lib.ntu.edu.tw/bitstream/246246/200704191002985/1/01206333.pdf
SDGs
[SDGs]SDG7
Type
conference paper
File(s)
Loading...
Loading...
Download
Name
01206333.pdf
Size
222.28 KB
Format
Adobe PDF
Checksum
(MD5):068f05e962dff6a74f3e6a6a8b064037
