An IR Drop Aware Test Pattern Generation Technique for Test Quality Enhancement
Date Issued
2014
Date
2014
Author(s)
Tsai, Li-Chen
Abstract
In general, power dissipation in test mode is higher than that in functional mode due to high switching activity. Severe IR drop caused by high power dissipation needs to be avoided because it may increase gate delay. Test environment with high power dissipation is too strict so that it may fail a good chip and then cause an overkill. Several low-power testing researches have been proposed to avoid from overkill by reducing switching activity. However, reducing too much switching activity may lead test environment to become loose. A test with loose environment may pass a faulty chip and then cause a test escape. This thesis proposed an IR drop aware test pattern generation technique. The functional-like test patterns generated with the proposed technique induced similar IR drop distributions to those induced by functional patterns. Experimental results showed that pattern count inflation, caused by applying the proposed technique, was very small, and had very low coverage loss.
Subjects
test pattern
IR drop
overkill
test escape
test quality
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-103-R01943088-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):af8ecaaf47004966adc05b33772b21fb