Parallel Multiple Stages Power Amplifier and Power Combining Technique
Date Issued
2006
Date
2006
Author(s)
Lin, Po-Tsung
DOI
en-US
Abstract
In this thesis, some different classifications and efficiency enhancement techniques of power amplifiers are introduced. Furthermore, some CMOS and SiGe power amplifiers used for wireless communication applications are designed and fabricated. For 0.18μm self-biased cascade CMOS power amplifier, it achieves 15.3 dB linear gain, 18.8 dBm Psat, 17.7 dBm P1dB, and 25.6 % PAE@P1dB; For 0.35μm parallel multiple power-stages SiGe power amplifier, in simulation, it achieves 28.7 dB linear gain, 28.9 dBm Psat, 26.6 dBm P1dB, and 41 % PAE@P1dB in high power stage, and 27.5 dB linear gain, 22.3 dBm Psat, 21.8 dBm P1dB, and 31.6 % PAE@P1dB in low power stage; For 0.35μm SiGe power amplifier with power combiner, it achieves 14 dB linear gain, 28.5 dBm Psat, 27.9 dBm P1dB, and 22.6 % PAE@P1dB. In addition, each design concepts and flows of these power amplifiers with different structures and the measurement method with PCB module are described in this thesis.
Subjects
並聯多級
功率放大器
功率結合技術
Parallel Multiple Stages
Power Amplifier
Power Combining Technique
Type
thesis
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