A Low-Power Analog Correlator for DS-CDMA System
Date Issued
2005
Date
2005
Author(s)
lo, Yen-Hung
DOI
en-US
Abstract
When wired local area networks speeds up to Gbps and 10 Gbps, wireless local area networks (WLAN) raises its data rate at the same time. IEEE had established two sets of communication protocol of wireless networks which are 802.11a and 802.11b respectively in 1999. Among them, the operating frequency of 802.11b is used by the frequency band within 2.4 GHz and the modulation types are CDMA and CCK. Up to now, it is the standard in mainstream market. However, the frequency band within 2.4 GHz is full of every kind of communication standards and therefore the frequency band within 5 GHz can be used to transmit some of mid-speed and low-speed data. The goal is to achieve the consideration of low power and some research centers and collages in foreign countries are proceeding similar projects like UC Berkeley wireless research center having a similar ultra low-power wireless networks plan. It is clear that the low-power wireless communication is the trend in the future.
In this thesis, we will focus on the correlator of analog front-end processor in wireless communication system to achieve our goal of low power. Designed in a 0.18-μm technology and powered 1.5-V supply voltage, the analog correlator operates at 16-MHz clock-rate while dissipating 0.04 mW. Besides, matching up to the architecture of analog correlator, we have simulated the synchronous strategy by multiple-dwell detection and obtained shorter acquisition time but proper degree of accuracy during acquisition.
Subjects
相關器
直接序列分碼多工
correlator
DS-CDMA
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-94-R91943078-1.pdf
Size
23.31 KB
Format
Adobe PDF
Checksum
(MD5):96065b225f2ae741c7e66e531fe81f80