A Study on Video Decoder Architecture
Date Issued
2007
Date
2007
Author(s)
Chen, Po-Hung
DOI
en-US
Abstract
The high coding efficiency of the latest video coding technique outperforms the previous video coding standards from many new features, including sub pixel inter prediction with variable block size and multiple reference frames, intra prediction, and deblocking.
However, its overall computational complexity also increases greatly such that a decoder requires two times the computational power of a MPEG-4 decoder and four times of a MPEG-2 decoder. Hence, it is necessary to design a hardware accelerator for video decoder.
This dissertation presents the design methodology for video decoder. An efficient and scalable macroblock level pipeline architecture is proposed to support video decoding functions. The proposed decoder is composed of decoding modules. Due to the complex, sequential, and highly data dependent characteristics of all essential algorithms, not only the pipeline structure but also efficient memory hierarchy are required. The decoding modules process in parallel via accessing data and control in local memory buffer.
In addition to the interface and design of the whole decoding architecture, three decoding modules including deblocking module, residue reconstruction module and motion compensation module are presented. The design flow for each module is a top-down design methodology. Based on the analysis of the specification, the detailed architectural algorithm flow for each module is explored. And, the analysis of the requirements for the performance and bandwidth to design each module is calculated. Then, all required design parameters are defined to implement those modules. The information can be used to decide all required I/O, data flow to implement an architecture of a module.
Subjects
視訊解碼器
架構
Video decoder
Architecture
Type
thesis
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