Design and Implementation of High-speed Continuous Time-to-Digital Converter Using Multiphase Sampling Technique
Date Issued
2007
Date
2007
Author(s)
Sung, Chih-Wei
DOI
en-US
Abstract
The main purpose of this thesis lies in the design and implementation of a Time-to-Digital Converter (TDC) which is also named as Time Digitizer. It is used to measure the pulse width of a single-shot pulse or the time interval between Start and Stop signals. The former signal, a single-shot pulse, the rising and falling edges can also be treated as the Start and Stop signals, respectively. The main principle and some definitions are similar as an Analog-to-Digital Converter (ADC). In recent years, Delay Locked Loops (DLLs) are widely used in many timing applications, such as clock generator、clock skew, etc. Due to the considerations of design facility and stability, DLLs are generally employed in modern TDC design.
The thesis is divided into two parts. The first part of the research is to realize continuous conversion time digitizer circuitry. Two-level conversion scheme is proposed in this part. Continuous signals propagate and are digitized at the same time without any reset mechanism. The concept of relative timing conversion is in replace of additional digital circuits. The conversion time is within a period of the reference clock to achieve the characteristic of high-speed operation. Mentioned to the circuit field, a novel edge combiner is proposed to multiply the external reference clock to the higher one which is served as the clock of the latter stage circuitry. It does not require any extra input clock for most portable usage. The chip is fabricated in 0.18-um CMOS 1P6M technology. With an input reference clock of 200MHz and a continuous signal of the maximum frequency of 400MHz, the proposed TDC achieves 78.125ps resolution. It simply adopts 16 delay elements to attain the interpolation ratio of 64. From the measurement results, the INL is within -0.99 LSB to 0.98 LSB and DNL is within -0.62 LSB to 0.51LSB. The whole chip roughly occupies the area of 1.1mm2.
The second part of this thesis focuses on higher resolution. It uses a phase interpolator to reach higher resolution. With an input reference clock of 400MHz and a continuous signal of the maximum frequency of 300MHz, the second design adopts only 12 delay elements to achieve the interpolation ratio of 128. It covers all of the above advantages and maintains its features of continuous sampling and relative timing conversion. This design is realized in 0.18-um CMOS 1P6M technology. The resolution increases 400% to 19ps. As to power dissipation, it requires only 50% of the previous work to 78mW. In the performance of linearity, the INL is within -1.19 LSB to 1.45 LSB and DNL is within -0.69 LSB to 0.79LSB. Such a high resolution TDC will be the main character on timing measurement in the future.
Subjects
時間至數位轉換器
延遲鎖定迴路
多相位產生器
邊緣合成器
連續轉換
Time-to-Digital Converter (TDC)
Delay Locked Loop (DLL)
edge combiner
Type
thesis