Multilevel routing with antenna avoidance.
Journal
Proceedings of the International Symposium on Physical Design
Pages
34-40
Date Issued
2004
Author(s)
Abstract
As technology advances into the nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high density plasma. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. In this paper, we propose a novel framework for multilevel full-chip routing with antenna avoidance using a built-in jumper insertion approach. Experimental results show that our approach reduced antenna-violated gates by about 98% and also achieved 100% routing completion for all circuits.
Subjects
Design for manufacturability (DFM); Multilevel optimization; Nanometer; Physical design; Process antenna effect; Routing
Other Subjects
Antennas; Computer aided design; Gates (transistor); Integrated circuit layout; Microprocessor chips; Routers; Design for manufacturability (DFM); Physical design; Process antenna effects; Routing; VLSI circuits
Type
conference paper