124Ms/s pixel-pipelined motion-JPEG 2000 codec without tile memory
Journal
IEEE International Solid-State Circuits Conference
Pages
1586-1595
Date Issued
2006
Author(s)
Chang, Yu-Wei
Fang, Hung-Chi
Cheng, Chih-Chi
Chen, Chun-Chia
Lian, Chung-Jr
Chen, Liang-Gee
Abstract
A JPEG2000 codec capable of processing 1920times1080 HD video at 30frames/s is implemented on a 20.1mm 2 die with 0.18μm CMOS technology dissipating 345mW at 1.8V and 42MHz. The level-switched schedule eliminates the 192kB tile memory. Hardware sharing between encoder and decoder reduces silicon area by 40%
SDGs
Type
conference paper
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