A hierarchical analysis methodology for chip-level power delivery with realizable model reduction
Journal
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Journal Volume
2003-January
Pages
614-618
Date Issued
2003
Author(s)
Lee, Y.-M.
Abstract
In this paper, we propose a novel hierarchical analysis methodology to facilitate efficient chip-level power fluctuation analysis. With extreme efficiency and simplicity, our design methodology first builds time-varying multiport Norton equivalent circuits in a row-by-row or block-by-block basis, followed by global analysis of the integrated reduced models. After generating the Norton equivalent sources at external ports, we apply realizable model order reduction technologies to further reduce the model. Since the elements of our reduced model are also RC devices, they are fully compatible with general circuit simulation engines. The experimental results demonstrate more than 4/spl times/ speed up with the flat simulation while maintaining within 5% accuracy.
Type
conference paper