A hierarchical analysis methodology for chip-level power delivery with realizable model reduction

Journal

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Journal Volume

2003-January

Pages

614-618

Date Issued

2003

Author(s)

Lee, Y.-M.

CHUNG-PING CHEN

DOI

10.1109/ASPDAC.2003.1195098

URI

https://scholars.lib.ntu.edu.tw/handle/123456789/501008

URL

https://www.scopus.com/inward/record.uri?eid=2-s2.0-84954455108&doi=10.1109%2fASPDAC.2003.1195098&partnerID=40&md5=19bd6839f7372a752bf4dcfd36657511

Type

conference paper