Subharmonically injection-locked PLLS for ultra-low-noise clock generation
Journal
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Date Issued
2009
Author(s)
Abstract
High-speed low-noise clocks are essential in numerous applications. In this paper, complete analysis and validation of subharmonic injection locking that can substantially reduce the PLL phase noise at negligible cost is presented. Two 20 GHz PLLs based on this technique demonstrate 149 and 85 fs rms jitter while consuming 38 and 105mW, respectively.
SDGs
Type
conference paper