Design of Millimeter-wave High Sideband Suppression Ratio Modulator for High Speed Transmission System and D-band Power Amplifier
Date Issued
2012
Date
2012
Author(s)
Liao, Hsin-Chiang
Abstract
This thesis is composed of two main researches. The first part is the investigations on two V-band I/Q modulators including the improvements on passive components and a creative method to enhance the I/Q balance, and the other part is the design topic about sub-millimeter-wave power amplifier.
The first part starts with a V-band wideband I/Q modulator implemented in TSMC 90-nm CMOS process. In order to improve the I/Q mismatch in the design of quadrature phase, a co-planar waveguide (CPW) interdigitated coupler with low amplitude and phase imbalances and insusceptibility to port impedance is employed. The LO leakage is also effectively mitigated by revising the conventional Marchand-type baluns with incomplete ground plane. Another I/Q modulator fabricated in WIN’s 0.15-um pHEMT technology features wideband sideband suppression ratio with the novel power-level calibration method, power-locked loop system. A feedback mechanism is introduced to improve I/Q mismatch automatically and also overcomes the bandwidth restriction on conventional couplers. The two proposed I/Q modulators demonstrate lower than -28 and -35 dBc sideband suppression ratio, respectively, with wider than 17 GHz bandwidth. Moreover, the capability to minimize the I/Q mismatch contribution to system error vector magnitude (EVM) is verified by 7 Gb/s high speed transmission experiments.
The second part presents the proposed impedance transformation network exemplified by a D-band power amplifier in TSMC 65-nm CMOS. In order to increase the output power and enhance the efficiency, the impedance transformation network integrates matching and power combining network simultaneously and also provides the solution of multi-ways power combining. The large impedance transformation ratio resulting from multi-way power combining can also be resolved in the procedure of proposed impedance transformation network. This can be verified by the small signal bandwidth of wider than 30 GHz. Furthermore, without additional power combining structures, higher than 12 dBm saturation power and 12 % power-added efficiency (PAE) are achieved with a compact chip size around 150 GHz.
Subjects
I/Q modulator
V-band
CPW coupler
Marchand balun
power-locked loop
sideband suppression
high speed transmission
power amplifier
D-band
impedance transformation
power combining
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-101-R99942028-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):dcffe39708ebfddafa7a4a426149ceb4