Fabrication of ZnO Thin Film Transistor and TCAD Model of the Devices

Recently, metal-oxide materials have drawn a lot of attention in research field. ZnO is suitable for room-temperature process. It has lots of advantages such as high transparency in the visible light region, and high electron mobility. Thus ZnO is regarded as a potential material for flexible electronics and panel displays. However, due to the fabrication process at room temperature, ZnO-based devices have lower stability than Si-based transistors. Moreover, since the material property of ZnO is unique and different from Si, the analysis of ZnO-based devices is more difficult, compared with traditional transistors. In this work, we demonstrate high-performance ZnO-based thin film transistors fabricated at room temperature. The operating current is 1.4 mA at VGS = 6V and VDS = 20V. The Ion-Ioff ratio is higher than 1.0×106. We also make a discussion on the problems encountered in fabricating ZnO-based TFT at room temperature. And then based on the grain boundary theory, we build a model. With this model, we can completely describe the carriers transport mechanism in the channel layers of ZnO-based TFTs fabricated at room temperature. First of all, we analyze ZnO TFTs with poor electrical properties. Hysteresis can be observed from IDS-VG curves and C-V curves of these devices. We also find out overshoots in IDS-VDS curves. In the first part of this thesis, in order to explain the hysteresis observed from transfer curves, the C–V profiles are described by qausi-static capacitance-voltage (QSCV) measurement in deferent integration time and from different sweep directions. According to the measurement results, the hysteresis I-V curves and C-V curves is result from the mobile ionic charges in the insulating layer. In the second part of this thesis, we use a model based on the theory of grain boundary to explain overshoots observed in the I-VDS curves. We verify the nanocrystalline property of ZnO thin film by X-ray diffraction (XRD) pattern and atomic force microscopy (AFM) image. Meanwhile, we use the “high-low-frequency capacitance method” to calculate the trap density in the channel layer. Finally, using parameters from the experimental results, we demonstrate an analytical IDS-VDS model in this work.