Verification Environment of High-Speed Serial Bus System

As the complexity of IC designs and price to tape-out increase, verification has become a vital step in the design flow. Debugging in a large and complicated system by waveform is both time and human resource consuming. Therefore, the time to market will increase.

This thesis introduces several verification skills, which includes transactionbased, assertion-based, simulation-based and coverage-based methods. These skills not only can be used to develop a verification environment, but also confirm the design is fit in with designer's hope and the requirement of specification. Furthermore, we use Verilog with Verification Language Extension (VLE) toolkits to model bus functional model (or so-called transaction verification model) and link monitor which make Design Under Test (DUT) integration easier and test case development more quickly.

PCI Express is a high-speed serial bus protocol and becomes an industry trend on work stations or personal computers. This high-speed point-topoint serial bus will soon replace current legacy shared parallel buses. In [2], the speed per lane/second/side is doubled and has more challenges. The goal of this thesis is to create a test environment which is aimed at PCI Express 2.0 platform. According to the experimental results, the functional coverage is very high. Design engineers and verification engineers can have more confidence in their design after verifying their design using this verification tool.