A 10-bit 300 MS/s pipeline ADC with time-domain MDAC
Journal
Analog Integrated Circuits and Signal Processing
Date Issued
2021
Author(s)
Abstract
A 10-bit 300?MS/s pipeline ADC utilizing time-domain MDAC is presented. The time-domain MDAC using only current sources and comparators to execute both signal subtraction and amplification is proposed to realize an opamp-less power-efficient structure without calibration. At the conversion rate of 300?MS/s with Nyquist input frequency, the ADC simulated in 40-nm CMOS exhibits an ENOB of 9.38 and 7.96 bits without and with device noise, respectively. It dissipates 19?mW at 1.2?V supply, where one-third of the power is consumed by the low-noise comparator. The noise analysis of the proposed time-domain MDAC is addressed. The active area of the ADC is 0.1?mm2. ? 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
Subjects
Analog to digital conversion; Comparator circuits; Comparators (optical); Operational amplifiers; Pipelines; Conversion rates; Current sources; Input frequency; Low noise comparators; Noise analysis; Pipeline ADCs; Power efficient; Signal subtraction; Time domain analysis
Type
journal article