Analysis and Design of Phase-Locked Loops for Reducing Spur and Dynamic Sensitivity
Date Issued
2012
Date
2012
Author(s)
Chen, Yu-Cheng
Abstract
In addition to the phase noise, the output signal of a phase-locked loop (PLL) includes the unwanted spur. The spectral purity of the output signal is determined by the two types of noise. In wireless communication receivers, the spur is a troublesome problem, affecting the signal to noise ratio. The easiest approach to improving the spur performance is to reduce the loop bandwidth. However, this solution affects the phase noise characteristic of the output signal. Another straightforward solution is to decrease the gain of the voltage-controlled oscillator (VCO). The drawback is that this solution limits the operation range of the VCO.
This dissertation presents a loop filter design method to achieve the spur reduction without having to decreasing the loop bandwidth, while considering the loop delay effects. Using control system theory, the dissertation solves the loop filter design problem in the z-domain and proposes an LMI-based method for the spur reduction. This method is applicable to both the third- and fourth-order charge-pump phase-locked loops. Compared to the conventional methods, the proposed method offers greater spur reduction without altering the loop bandwidth.
The performances of PLLs mainly depend on the dynamic parameters: the loop bandwidth and the jitter peaking. For example, the loop bandwidth plays an important role in trade-off between the in-band phase noise and the out-of-band phase noise. The jitter peaking directly affects the loop stability. Due to process, voltage, and temperature (PVT) variations, the actual values of the passive components, the VCO gain and the charge-pump current will differ from their designed values. Therefore, the actual dynamic parameters are rarely equal to their well-designed values. This affects the performances of the system.
Using a z-domain PLL model, this dissertation presents an analysis method to explore the effects of the loop filter pole on the dynamic parameter changes. Based on the results of the analysis, we propose a design strategy. Compared to the conventional method, this strategy would lessen the effects of the PVT variation on the dynamic parameter and improve the spur performance when the dynamic parameter changes are dominated by the resistor and large phase margin is required.
Subjects
Jitter peaking
Loop delay
Linear matrix inequality (LMI)
Loop bandwidth
Phase-locked loop (PLL)
Reference spur
PVT variation
z-domain
Type
thesis
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