A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization
Journal
Solid-State Circuits Conference (ISSCC)
Pages
356-357
Date Issued
2011-02
Author(s)
Yi-Chieh Huang
Abstract
To ensure the signal integrity over a lossy channel, an analog equalizer and/or a decision-feedback equalizer (DFE) [2-6] are widely adopted in high-speed data transmission. An adaptive analog equalizer or adaptive DFE is also attractive to compensate the frequency-dependent loss due to the different channel lengths and environment variations. Conventionally, a multiple-tap DFE is adopted to compensate the inter-symbol interference (ISI), which is induced by postcursors due to the non-ideal channel impulse responses. To avoid the power and area penalty due to many postcursors, a DFE with infinite impulse response (IIR) filter feedback [2] has been presented. In [2], no adaptation scheme ensures that such IIR filter cancels the postcursors precisely, i.e., its RC time constant and amplitude need to be manually adjusted. In this work, a 6Gb/s receiver using a DFE with an adaptive continuous-time IIR filter and a clock/data recovery (CDR) circuit is presented. In a high loss environment, a conventional digital qaudricor-relator frequency detector (QFD) may fail due to the significant data dependent jitter. To integrate an adaptive DFE with a CDR circuit, a proposed frequency-sweeping frequency detector (FD) and a lock detector (LD) are presented in this work. © 2011 IEEE.
SDGs
Other Subjects
Clock and data recovery circuits (CDR circuits); Continuous time systems; Decision feedback equalizers; Feedback; Impulse response; Channel impulse response; Data-dependent jitter; Frequency detectors; Frequency sweeping; Frequency-dependent loss; High-speed data transmission; Infinite impulse response; RC time constants; IIR filters
Type
conference paper