Parallel global elimination algorithm and architecture design for fast block matching motion estimation
Resource
Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04). IEEE International Conference on
Journal
IEEE International Conference on Acoustics, Speech, and Signal Processing, 2004. (ICASSP '04).
Pages
-
Date Issued
2004-05
Date
2004-05
Author(s)
DOI
1520-6149
Abstract
The critical path of the hardware for the global elimination algorithm (GEA) is too long to meet the real-time constraints for high-end applications. In this paper, we propose a new parallel GEA and its corresponding architecture. By dividing candidate blocks into independent groups and finding the most probable candidates of each group in parallel, instead of sequentially searching within the whole search range, parallel design can be developed as an array of GEA processing elements with much shorter critical path. Besides, the GEA processing element is optimized to reduce 30% of the gates, and the 2D data reuse is organized to save 80% of the SRAM bandwidth, which also reduces a lot of power. Simulation results show that our implementation can achieve real time processing of D1 30 Hz video with search range as H[-64, +63.5] V[-32, +31.5] while the operating frequency is 70 MHz, and the gate count is 113 K. Compared with full search, our gate count is six times smaller under the same frequency, and the PSNR loss is at most 0.1-0.2 dB.
Type
journal article
File(s)![Thumbnail Image]()
Loading...
Name
01327070.pdf
Size
314.89 KB
Format
Adobe PDF
Checksum
(MD5):b0b9b427d51c267b54b06895ae66f8d9