New Front-end DSP Algorithms and VLSI Architectures for Cost-efficient Communication Receiver IC Designs
Date Issued
2007
Date
2007
Author(s)
Lai, Jyh-Ting
DOI
en-US
Abstract
The mixed-signal design is a widely employed approach in communication IC design because it can benefit low hardware complexity and less chip-to-chip interfaces. The difficulties of mixed-signal design are often the interface components or signals between analog and digital circuits. These are many digital processing technologies to handle the interface signaling or controlling the analog components. We summarize these kinds of design/technology as the “Front-end Digital Signal Process” (Front-end DSP). In the thesis, we will define and discuss the designs of the Front-end DSP in both wireline and wireless communication systems.
We firstly analyze the difficulties and issues of Front-end DSP for wireline and wireless applications. For wireline communication, we study the automatic gain control (AGC) and the equalizer in the Front-end DSP. Traditional approaches of AGC involve estimating the average power or the peak amplitude over an extended period, which results in high hardware complexity and a time-consuming evaluation. Moreover, the accuracy of traditional approaches is seriously degraded by noise and intersymbol interference (ISI). In this thesis, we propose a joint AGC and equalization (Joint AGC-EQ) scheme, in which the digital control unit (DCU) circuitry comprises only one-tenth of the area of a traditional AGC and the output power of the variable-gain amplifier can reach the optimal peak-to-average power ratio under different ISI environments. In addition, we provide a closed-form analysis of the convergence of the scheme, which shows that the total convergence time of Joint AGC-EQ is only half that of traditional blind equalization. The scheme is already silicon-proven for the application of a Fast Ethernet transceiver using Faraday/UMC 0.18-μm cell libraries. Experiments have revealed that the bit error rate is much better than the 802.3u specification, and that the scheme passes the stringent Killer Pattern testing of the University of New Hampshire InterOperability Laboratory.
For wireless communication system, we study the automatic gain control (AGC) and the paceket detector (PD) of the Front-end DSP in Multiband orthogonal frequency-division multiplexing (MB-OFDM) system. The MB-OFDM systems employ frequency-hopping technology to achieve the capabilities of multiple access and frequency diversity. However, they also complicate the PD and time-frequency code synchronization, in terms of the requirement for fast synchronization for the frequency hopping, the extremely low receiver sensitivity, and the high hardware complexity. In this part, we systematically analyze the differences between MB-OFDM and conventional OFDM systems, and then propose a band tracking PD (BT-PD) that can cope with a worse-case multipath channel SNR of –8.4 dB with a packet detection error rate of less than 10–5. We also propose several low-cost design schemes for the BT-PD, such as Walsh-Hadamard decomposition, buffered summation, and sign-bit-remaining methods. The estimated gate count of the resulting implemented BT-PD is less than half that of existing solutions.
In summary, we study the key components in Front-end DSP of both wireline and wireless communication systems. These components are very crucial but seldom discussed in previous researches. Our systematic approaches of the Front-end DSP can achieve the goals of PAPR optimization, low hardware complexity and better performance in mixed-signal baseband IC design.
Subjects
自動增益控制器
等化器
多頻道正交頻率多工系統
正交頻率多工系統
封包檢測器
Automatic Gain Control
AGC
Equalizer
MB-OFDM
OFDM
Packet Detector
Type
thesis
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